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low emi spectrum spread clock fs781/82/84 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07029 rev. *f revised january 2, 2005 features ? spread spectrum clock generator (sscg) with 1, 2, and 4 outputs ? 6- to 82-mhz operating frequency range ? modulates external clocks including crystals, crystal oscillators, or ceramic resonators ? programmable modulation with simple r-c external loop filter (lf) ? center spread modulation ? 3v-5v power supply ? ttl-/cmos-compatible outputs ? low short-term jitter ? low-power dissipation ? 3.3 vdc = 37 mw ? typical ? 5.0 vdc = 115 mw ? typical ? available in 8-pin soic and tssop packages applications ? desktop/notebook computers ? printers, copiers, and mfp ? scanners and fax ? lcd displays and monitors ? cd-rom, vcd, and dvd ? automotive and embedded systems ? networking, lan/wan ? digital cameras and camcorders ?modems benefits ? programmable emi reduction ? fast time to market ? lower cost of compliance ? no degradation in rise/fall times ? lower component and pcb layer count functional description the cypress fs781/82/84 are spread spectrum clock generator ics (sscg) designed for the purpose of reducing electromagnetic interference (emi) found in today?s high-speed digital systems. the fs781/82/84 sscg clocks use a cypress-proprietary technology to modulate the input clock frequency, xin, by modulating the frequency of the digital clock. by modulating the reference clock the measured emi at the fundamental and harmonic frequencies of fsout is greatly reduced. this reduction in radiated energy can significantly reduce the cost of complying with regulatory requirements without degrading digital waveforms. the cypress fs781/82/84 cl ocks are very simple and versatile devices to use. by programming the two range select lines, s0 and s1, any frequency from 6- to 82-mhz operating range can be selected. t he fs781/2/4 are designed to operate over a very wide range of input frequencies and provides 1, 2, and 4 modulated clock outputs. the fs78x devices have a simple frequency selection table that allows operation from 6 mhz to 82 mhz in four separate ranges. the bandwidth of the frequency spread at fsout is determined by the values of th e loop filter components. the modulation rate is determined internally by the input frequency and the selected input frequency range. the bandwidth of these produ cts can be programmed from as little as 1.0% up to as much as 4.0% by selecting the proper loop filter value. refer to the loop filter selection chart in table 2 and table 3 for the recommended values. due to a wide range of application requir ements, an external loop filter (lf) is used on the fs78x products. the user can select the exact amount of frequency modulation suitable for the appli- cation. using a fixed internal loop filter would severely limit the use of a wide range of modulation bandwidths (spread %) to a few discrete values. refer to fs791/2/4 products for appli- cations requiring 80- to 140-mhz frequency range. [+] feedback
fs781/82/84 document #: 38-07029 rev. *f page 2 of 12 output frequency selection loop filter selection chart the following table provides a list of recommended loop filter values for the fs781/82/84. the fs78x is divided into four ranges and operated at both 3. 3v and 5.5 vdc. the loop filter at the right is representative of the loop filter components in table 2 . pin description pin name i/o type description 1/2 (soic) 3/4 (tssop) x in /x out i/o analog pins form an on-chip re ference oscillator when connected to terminals of an external parallel resonant crystal . x in may be connected to ttl/cmos external clock source. if x in is connected to an external clock other than crystal, leave x out (pin 2) unconnected. 7/3 (soic) 1/5 (tssop) s0 / s1 i cmos/ttl digital control inputs to select input frequency range and output frequency scaling . refer to ta ble 2 and table 3 for selection. s0 has internal pull-down. s1 has internal pull-up. 4 (soic) 6 (tssop) lf i analog loop filter . single ended three-state output of the phase detector. a two-pole passive loop filter is connected to lf. 6 (soic) 8 (tssop) fsout o cmos/ttl modulated clock frequency output . the center frequency is the same as the input reference frequency for fs781. input frequency is multiplied by 2 and 4 for fs782 and fs784, respectively. 8 (soic) 2 (tssop) v dd p power positive power supply . 5 (soic) 7 (tssop) v ss p power power supply ground . table 1. fsout sscg (modulated output clock) product selection product number fsout frequency scaling description fs781 1 1 modulated frequency of input clock fs782 2 2 modulated frequency of input clock fs784 4 4 modulated frequency of input clock block diagram pin configuration phase detector vco 1(3) 2(4) xin xout 10 pf. reference divider 8 pf 8 pf 250 k vco / n modulation control input control logic output divider and mux power contol logic 3(5) 7(1) 8(2) 5(7) 4(6) vdd s0 s1 fsout loop filter vss 6(8) vss vdd (tssop pin #) 1 2 3 4 8 7 6 5 xin xout s1 lf vdd s0 fsout vss fs78x 8 pin soic package 1 2 3 4 8 7 6 5 s0 vdd xin xout fsout vss lf s1 fs78x 8 pin tssop package c8 r6 c7 lf (pin 4) [+] feedback
fs781/82/84 document #: 38-07029 rev. *f page 3 of 12 table 2. fs781/82/84 recommended loop filter values c7 (pf) @ +3.3 vdc 5% (r6 = 3.3k) [1, 2, 3, 4] input mhz s1 s0 bw = 1.0% [3] bw = 1.5% [3] bw = 2.0% [3] bw = 2.5% [3] bw = 3.0% [3] bw = 3.5% [3] bw = 4.0% [3] 6 0 0 10,000/1000 1550 910 780 700 640 560 8 0 0 10,000/330 990 820 640 520 450 400 10 0 0 1040 680 460 360 300 240 210 12 0 0 830 420 300 220 200 190 170 14 0 0 580 230 200 160 140 100 80 16 0 1 10000 980 760 580 470 410 385 18 0 1 1200 750 580 470 415 370 300 20 0 1 1000 730 470 390 320 220 190 22 0 1 960 640 410 270 230 200 180 24 0 1 920 400 250 210 180 160 150 26 0 1 660 300 220 180 150 140 120 28 0 1 470 230 180 150 130 100 70 30 0 1 470 180 140 120 100 80 60 32 0 1 330 170 120 100 82 68 47 34 1 0 10000 860 640 520 430 380 330 36 1 0 2200 820 620 470 400 330 290 38 1 0 1500 690 520 410 340 290 240 40 1 0 960 600 420 340 280 220 160 42 1 0 940 620 380 275 230 210 180 44 1 0 950 680 400 250 210 190 170 46 1 0 900 580 270 220 190 180 165 48 1 0 790 440 260 210 180 160 140 50 1 0 660 360 250 190 170 150 140 52 1 0 470 325 220 185 155 135 120 54 1 0 470 270 200 170 140 130 100 56 1 0 445 250 185 150 120 85 47 58 1 0 430 210 165 130 100 65 33 60 1 0 295 185 150 120 100 90 82 62 1 0 270 220 150 120 100 82 68 64 1 1 1180 860 560 410 340 290 230 65 1 1 1180 850 540 400 330 280 220 66 1 1 1180 760 560 350 260 220 210 68 1 1 1180 750 500 320 260 230 210 70 1 1 1120 740 470 370 300 240 170 72 1 1 1160 780 470 300 250 220 190 74 1 1 1110 770 470 280 230 210 190 76 1 1 1000 720 440 240 210 190 170 78 1 1 910 670 270 210 190 170 160 80 1 1 900 620 260 210 190 170 156 82 1 1 900 540 250 210 190 170 150 notes: 1. if the value selected from the above chart is not a standard, use the next available larger value. 2. all bandwidths indicated above are total peak-to-peak spread. 1% = +0.5% to ?0.5%. 4% = +2.0% to ?2.0%. 3. if c8 is not listed in the chart for a particular ba ndwidth and frequency, it is not used in the loop filter. 4. contact cypress for lf values less than 1.0% bandwidth. [+] feedback
fs781/82/84 document #: 38-07029 rev. *f page 4 of 12 table 3. fs781/82/84 recommended loop filter values c7 (pf) @ +5.0 vdc 5% (r6 = 3.3k) [1, 2, 3, 4] input mhz s1 s0 bw = 1.0% [3] bw = 1.5% [3] bw = 2.0% [3] bw = 2.5% [3] bw = 3.0% [3] bw = 3.5% [3] bw = 4.0% [3] 6 0 0 1140 1030 930 830 710 610 510 8 0 0 1170 970 740 570 460 400 280 10 0 0 1030 660 430 350 280 210 130 12 0 0 760 340 230 200 180 160 130 14 0 0 450 240 180 140 100 70 50 16 0 1 2490 970 730 590 480 430 370 18 0 1 2490 870 650 510 430 370 310 20 0 1 1360 680 480 370 280 190 250 22 0 1 990 560 330 260 230 200 190 24 0 1 820 360 250 200 180 160 150 26 0 1 530 270 210 170 150 110 90 28 0 1 430 230 180 150 110 100 90 30 0 1 250 200 150 110 100 90 80 32 1 0 note 4 1000 740 570 470 410 370 34 1 0 note 4 990 710 520 420 360 300 36 1 0 note 4 970 670 480 380 310 230 38 1 0 note 4 880 560 380 310 270 220 40 1 0 note 4 800 460 290 240 230 220 42 1 0 1030 680 360 260 220 200 190 44 1 0 790 560 260 220 200 190 170 46 1 0 1110 420 280 210 180 170 140 48 1 0 1110 280 200 190 170 140 120 50 1 0 830 330 200 180 160 130 110 52 1 0 560 340 205 170 140 120 90 54 1 0 510 280 180 140 110 110 90 56 1 0 470 210 160 120 100 90 90 58 1 0 450 220 250 110 90 80 80 60 1 0 430 240 120 90 80 80 70 62 1 1 note 4 800 580 430 330 250 180 64 1 1 note 4 720 490 375 285 200 140 66 1 1 note 4 630 400 320 240 150 100 68 1 1 note 4 690 365 285 225 170 140 70 1 1 note 4 650 330 250 210 190 180 72 1 1 note 4 575 340 250 210 190 170 74 1 1 note 4 500 355 245 205 180 165 76 1 1 note 4 550 330 230 200 175 160 78 1 1 note 4 600 290 220 190 170 155 80 1 1 note 4 570 240 210 185 165 150 82 1 1 note 4 540 250 200 180 160 140 [+] feedback
fs781/82/84 document #: 38-07029 rev. *f page 5 of 12 sscg modulation profile the digital control inputs s0 and s1 determine the modulation frequency of fs781/2/4 products. the input frequency is divided by a fixed number, depending on the operating range that is selected. the modulation frequency of the fs78x can be determined from table 4 . to compute the modulation frequency, determine the values of s0 and s1, and find the modulation divider number in table 4 . theory of operation the fs781/82/84 devices are phase-locked loop-(pll)-type clock generators using direct digital synthesis (dds). ?by precisely controlling the bandwidth of the output clock, the fs781/2/4 products become a low-emi clock generator. the theory and detailed operation of these products will be discussed in the following sections. emi all clocks generate unwanted energy in their harmonics. conventional digi tal clocks are square waves with a duty cycle that is very close to 50%. because of the 50/50 duty cycle, digital clocks generate most of their harmonic energy in the odd harmonics (e.g., third, fifth, seventh). it is possible to reduce the amount of energy contained in the fundamental and harmonics by increasing the bandwidth of the funda- mental clock frequency. conventional digital clocks have a very high q factor, which means t hat all of the energy at that frequency is concentrated in a very narrow bandwidth, conse- quently, higher energy peaks. regulatory agencies test electronic equipment by the am ount of peak energy radiated from the equipment. by reducin g the peak energy at the funda- mental and harmonic frequencies, the equipment under test is able to satisfy agency requirements for emi. conventional methods of reducing emi have been to use shielding, filtering, multi-layer pcbs, etc. these fs781/2 and 4 reduce the peak energy in the clock by increasing the clock bandwidth and lowering the q of the clock. sscg the fs781/82/84 products use a unique method of modulating the clock over a very narrow bandwidth and controlled rate of change, both peak to peak and cycle to cycle. the fs78x products take a narrow band digital reference clock in the range of 6?82 mhz and produce a clock that sweeps between a controlled start and stop frequency and precise rate of change. to understand what happens to an sscg clock, consider that we have a 20-mhz clock with a 50% duty cycle. from a 20-mhz clock we know the following: clock frequency = fc = 20 mhz. clock period = tc = 1/20 mhz = 50 ns. consider that this 20-mhz clock is applied to the x in input of the fs78x as either an externally driven clock or the result of a parallel resonant crystal connected to pins 1 and 2 of the fs78x. also consider that the products are operating from a 5v dc power supply and the loop filter is set for a total bandwidth spread of 2%. refer to figure 2 . table 4. modulation rate divider ratios s1 s0 input frequency range (mhz) modulation divider number 0 0 6 to 16 120 0 1 16 to 32 240 1 0 32 to 66 480 1 1 66 to 82 720 xin + .5% - .5% time (microseconds) 1.0% total figure 1. frequency profile in time domain [5] note: 5. with the correct loop filter connected to pin 4, the following profile will provide the best emi reduction. this profile can be seen on a time domain analyzer. [+] feedback
fs781/82/84 document #: 38-07029 rev. *f page 6 of 12 from the above parameters, th e output clock at fsout will be sweeping symmetrically around a center frequency of 20 mhz. the minimum and maximum extremes of this clock will be +200 khz and ?200 khz. so we have a clock that is sweeping from 19.8 mhz to 20.2 mhz and back again. if we were to look at this clock on a spectrum analyzer we would see the picture in figure 3 . keep in mind that this is a drawing of a perfect clock with no noise. we see that the original 20-mhz reference clock is at the center frequency (cf), and the min. and max. extremes are positioned symmetrically about the center frequency. this type of modulation is called center-spread. figure 4 shows a 20-mhz clock as it would be seen on an oscilloscope. the top trace is the non-modulated reference clock. the bottom trace is the modulated clock at pin 6. from this comparison chart you can see that the frequency is decreasing and the period of each successive clock is increasing. the tc measurements on the left and right of the bottom trace indicate the max. and min. extremes of the clock. intermediate clock changes are small and accumulate to achieve the total period deviation. the reverse of this figure would show the clock going from minimum extreme back to the high extreme. looking at figure 3 , you will note that the peak amplitude of the 20-mhz non-modulated clock is higher than the wideband modulated clock. this difference in peak amplitudes between modulated and unmodulated clocks is the reason why sscg clocks are so effective in digita l systems. this figure refers to the fundamental frequency of a clock. a very important charac- teristic of the sscg clock is th at the bandwidth of the funda- mental frequency is multiplied by the harmonic number. in other words, if the bandwidth of a 20-mhz clock is 200 khz, the bandwidth of the third harmonic will be 3 200, or 600 khz. the amount of bandwidth is rela tive to the amount of energy in the clock. consequently, the wider the bandwidth, the greater the energy reduction of the clock. most applications will not have a problem meeting agency specifications at the fundament al frequency. it is the higher harmonics that usually cause the most problems. with an sscg clock, the bandwidth and peak energy reduction increases with the harmonic number. consider that the eleventh harmonic of a 20-mhz clock is 220 mhz. with a total spread of 200 khz at 20 mhz, the spread at the eleventh harmonic would be 2.20 mhz, wh ich greatly reduces the peak energy content. it is typical to see as much as 12- to 18-db reduction at the higher harmonics, due to a modulated clock. the difference in the peak ener gy of the modulated clock and the non-modulated clock in typical applications will see a 2?3db reduction at the fundamental and as much as 8 ? 10 db reduction at the intermediate harmonics: third, fifth, seventh, etc. at the higher harmonics, it is quite possible to reduce the peak harmonic energy, compared to the unmodu- lated clock, by as much as 12 to 18 db. application notes and schematic figure 5 is configured for the following parameters: package selected = fs781. x in = 20-mhz crystal fsout = 20 mhz (s0 = 1 and s1 = 0). bandwidth of the fsout clock is determined by the values of the loop filter connected to pin 4. 50% 50% tc = 50 ns. figure 2. 20-mhz unmodulated clock fc = 20 mhz fmin = 19.8 mhz fmax = 20.2 mhz figure 3. spectrum analysis of 19.8?20.2 mhz clock tc = 50.50 n tc =49.50 ns. figure 4. period comparison chart [+] feedback
fs781/82/84 document #: 38-07029 rev. *f page 7 of 12 ** ** occasionally, c8 is used to create a second pole for this loop filter. refer to loop filter selection table. mount loop filter components as close to lf pin as possible. . crystal is 20 mhz is 1st order with 18 pf load capacitance. if crystal load capacitance is different than 18 pf, c1 and c2 must be re-calculated. for third overtone crystals, a parallel or series resonant trap is required. r6 c1 0.1 uf c2 27 pf c3 27 pf y1 20 mhz c8 c7 fs781 (soic) xin 1 xout 2 s1 3 lf 4 vss 5 fsout 6 s0 7 vdd 8 vdd fsout figure 5. fs781 schematic [+] feedback
fs781/82/84 document #: 38-07029 rev. *f page 8 of 12 absolute maximum ratings [6] this device contains circuitry to protect the input against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of any voltage higher than the absolute maximum rated voltages to this circuit. for proper operation, v in and v out should be constrained to the range, v ss < (v in or v out ) < v dd . all digital inputs are tied high or low internally. refers to electrical speci- fications for operating supply range. table 5. absolute maximum ratings parameter description min. max. unit v dd operating voltage 3.0 6.0 vdc virvss input, relative to v ss ?0.3 v dd + 0.3 vdc vorvss output, relative to v ss ?0.3 v dd + 0.3 vdc top temperature, operating 0 +70 c tst temperature, storage ?65 +150 c t j temperature, junction ? +125 c table 6. dc electrical characteristics v dd = 3.3v and 5.0v 10%, x in = 48 mhz, t a = 0c to 70c parameter description min. typ. max. unit v il input low voltage ? 0.3 * v dd vdc v ih input high voltage 0.7 * v dd vdc i il input low current 100 a i ih input high current 100 a v ol output low voltage i ol = 10 ma, v dd = 5v 0.4 vdc v oh output high voltage i oh = 10 ma, v dd = 5v v dd ? 1.0 vdc v ol output low voltage i ol = 6 ma, v dd = 3.3v 0.4 vdc v oh output high voltage i oh = 5 ma, v dd = 3.3v 2.4 vdc rpd resistor, pull-down (pin 7) 60k 125k 200k ? rpu resistor, pull-up (pin 3) 60k 125k 200k ? c xin input capacitance (pin 1) 8 pf c xout output capacitance (pin 2) 10 pf i cc 5v dynamic supply current (c l = no load) 38 ma i cc 3.3v dynamic supply current (c l = no load) 20 ma isc short circuit current (fsout) 25 ma bw bw% variations, 3.30v [7] ?20 0 +20 % bw bw% variations, 5.00v [7] ?30 0 +30 % table 7. timing electri cal characteristics v dd = 3.3v and 5.0v 10%, t a = 0c to 70c, c l = 15 pf, x in = 48 mhz parameter description min. typ. max. unit ttlh output rise time measured at 10%?90% @ 5 vdc 1.8 2.2 2.7 ns tthl output fall time measured at 10%?90% @ 5 vdc 1.5 2.0 2.5 ns ttlh output rise time measured at 0.8v?2.0v @ 5 vdc 0.5 0.65 0.8 ns tthl output fall time measured at 0.8v?2.0 v @ 5 vdc 0.5 0.65 0.8 ns ttlh output rise time measured at 10%?90% @ 3.3 vdc 2.1 2.65 3.2 ns tthl output fall time measured at 10%?90% @ 3.3 vdc 1.7 2.1 2.6 ns ttlh output rise time measured at 0.8v?2.0v @ 3.3 vdc 0.7 0.95 1.2 ns tthl output fall time measured at 0.8v?2.0 v @ 3.3 vdc 0.6 0.85 1.1 ns tsymf1 output duty cycle 45 50 55 % notes: 6. single power supply : the voltage on any input or /o pin cannot exceed the power pin during power-up. 7. percentage variations from the bandwidth % values given in table 2 and table 3 . [+] feedback
fs781/82/84 document #: 38-07029 rev. *f page 9 of 12 ccj fsout, cycle-to-cycle jitter, 48 mhz @ 3.30 vdc (pin 6) ? 320 370 ps ccj fsout, cycle-to-cycle jitter, 48 mhz @ 5.0 vdc (pin 6) ? 310 360 ps ccj fsout, cycle-to-cycle jitter, 72 mhz @ 3.30 vdc (pin 6) ? 270 325 ps ccj fsout, cycle-to-cycle jitter, 72 mhz @ 5.0 vdc (pin 6) ? 390 440 ps table 7. timing electri cal characteristics v dd = 3.3v and 5.0v 10%, t a = 0c to 70c, c l = 15 pf, x in = 48 mhz (continued) parameter description min. typ. max. unit table 8. range selection table s1 (pin 3) s0 (pin 7) fin (mhz) (pin 2/3) modulation rate fs781 fsout (pin 6) fs782 fsout (pin 6) fs784 fsout (pin 6) 0 0 6?16 fin/120 6?16 mhz 12?32 mhz 32?64 mhz 0 1 16?32 fin/240 16?32 mhz 32?64 mhz 64?82 mhz 1 0 32?66 fin/480 32?66 mhz 64?82 mhz n/a 1 1 66?82 fin/720 66?82 mhz n/a n/a ordering information [8] part number package type product flow imifs781bzb 8-pin 150-mil soic commercial, 0 to 70 c imifs781bzbt 8-pin 150-mil soic ? tape and reel commercial, 0 to 70 c imifs782bzb 8-pin 150-mil soic commercial, 0 to 70 c imifs782bzbt 8-pin 150-mil soic ? tape and reel commercial, 0 to 70 c imifs784bzb 8-pin 150-mil soic commercial, 0 to 70 c imifs784bzbt 8-pin 150-mil soic ? tape and reel commercial, 0 to 70 c imifs781bt 8-pin (4.4 mm body) tssop commercial, 0 to 70 c imifs781btt 8-pin (4.4 mm body) tssop ? tape and reel commercial, 0 to 70 c imifs784bt 8-pin (4.4 mm body) tssop commercial, 0 to 70 c imifs784btt 8-pin (4.4 mm body) tssop ? tape and reel commercial, 0 to 70 c lead-free CYIFS781BSXC 8-pin 150-mil soic commercial, 0 to 70 c CYIFS781BSXCt 8-pin 150-mil soic ? tape and reel commercial, 0 to 70 c cyifs782bsxc 8-pin 150-mil soic commercial, 0 to 70 c cyifs782bsxct 8-pin 150-mil soic ? tape and reel commercial, 0 to 70 c cyifs784bsxc 8-pin 150-mil soic commercial, 0 to 70 c cyifs784bsxct 8-pin 150-mil soic ? tape and reel commercial, 0 to 70 c cyifs781bzxc 8-pin (4.4 mm body) tssop commercial, 0 to 70 c cyifs781bzxct 8-pin (4.4 mm body) tssop ? tape and reel commercial, 0 to 70 c cyifs782bzxc 8-pin (4.4 mm body) tssop commercial, 0 to 70 c cyifs782bzxct 8-pin (4.4 mm body) tssop ? tape and reel commercial, 0 to 70 c cyifs784bzxc 8-pin (4.4 mm body) tssop commercial, 0 to 70 c cyifs784bzxct 8-pin (4.4 mm body) tssop ? tape and reel commercial, 0 to 70 c note: 8. the ordering part number differs from the marking on the actual device. [+] feedback
fs781/82/84 document #: 38-07029 rev. *f page 10 of 12 marking example package drawing and dimensions cypress fs781bs date code, lot # cypress fs781bt date code, lot # fs781 b s cypress device driver revision package s = soic t = tssop seating plane pin1id 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.189[4.800] 0.196[4.978] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 1. dimensions in inches[mm] min. max. 0~8 0.016[0.406] 0.010[0.254] x 45 2. pin1idisoptional, round on single leadframe rectangular on matrix leadframe 0.004[0.102] 8 lead (150 mil) soic s08 1 4 58 3. reference jedec ms-012 part # s08.15 standard pkg. sz08.15 lead free pkg. 4. package weight 0.07gms 8-lead (150-mil) soic s8 51-85066-*c [+] feedback
fs781/82/84 document #: 38-07029 rev. *f page 11 of 12 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all product and company names mentio ned in this document may be the tr ademarks of their respective holders. package drawing and dimensions (continued) 8 pin1id seating plane 1 bsc. bsc 0-8 plane gauge 2.90[0.114] 1.10[0.043] max. 0.65[0.025] 0.20[0.008] 0.05[0.002] 6.50[0.256] 0.076[0.003] 6.25[0.246] 4.50[0.177] 4.30[0.169] 3.10[0.122] 0.15[0.006] 0.19[0.007] 0.30[0.012] 0.09[[0.003] 0.25[0.010] 0.70[0.027] 0.50[0.020] 0.95[0.037] 0.85[0.033] dimensions in mm[inches] min. max. 8-lead thin shrunk small outline package (4.40 mm body) z8 51-85093-*a [+] feedback
fs781/82/84 document #: 38-07029 rev. *f page 12 of 12 document history page document title: fs781/82/84 low emi spectrum spread clock document number: 38-07029 rev. ecn no. issue date orig. of change description of change ** 106948 06/07/01 ika convert from imi to cypress *a 111654 02/27/02 ikl add new marking suffix for soic packages. converted to framemaker. *b 118355 08/30/02 rgl swap the location of s0 and s1 in tables 2 and 3 in pages 2,3 and 4. *c 122679 12/14/02 rbi add power up requirements to operating conditions information. *d 277189 see ecn rgl added lead-free devices *e 314274 see ecn rgl fixed the ordering information to match the devmaster *f 417662 see ecn rgl added maximum junction temperature in absolute maximum ratings table [+] feedback

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